SOI (Silicon On Insulator) technology reduces or eliminates bulk CMOS latch-up problems. Additionally, SOI technology reduces junction capacitance and allows circuits to operate at higher speeds. Accordingly, SOI technology allows a higher circuit density to be achieved on a silicon wafer.
A multiple layer device structure can be created using SOI technology. Each level of a multilevel structure created using SOI may be interconnected using vertical plugs. Metal connections can be used at any level. In a multilevel device, NMOS and PMOS devices may each be restricted to a separate level, or NMOS and PMOS devices may be intermixed on a single level. However, having multiple levels where each level requires a set of separate metal connections may result in a large number of metal connections, increasing the complexity and costs of the chip. Furthermore, a layer of a multilevel device may inhibit cooling of adjacent layers by limiting heat transfer therefrom.
For some types of semiconductor devices, it is advantageous to have multiple layers of similar semiconductor material, where each layer has a crystal orientation different from the adjoining layers. When multi-layer devices are formed from a common semiconductor layer they will have the same crystal orientation from one level to the next. This limitation on the crystal orientation across multiple levels of an integrated circuit results from constraints imposed by the fabrication process.
In particular, semiconductor material is traditionally grown from a pre-existing layer of semiconductor material. During the material growth process, the atoms of the newly formed layer have a strong tendency to orient themselves to the pre-existing substrate's crystal structure as they are laid down. Thus, it becomes very difficult to create a new layer of similar semiconductor material having a crystal orientation which is different from the underlying layer.